The miniaturization of Field Effect Transistors (FET) for Logic and Memory applications highly depends on the effective control of short channel effects. To assess the scalability of specifc FET technologies, the concept of the screening or natural length λ in FET channels is commonly used. It is inspired from the Debye electrostatic screening length and is adapted to capture geometric and material features of the device studied in order to provide a metric for the gating efficiency of the channel. The intention is to derive the critical length along the charge transport direction required for the electronic bands of the semiconductor to react to the gate potential applied. The shorter λ is, the shorter the MOSFET channel length can be scaled without being critically affected by short channel effects.
A reduction of the MOSFET gate length below of ~ 30 nm requires an ultrathin thickness of the active semiconductor region and / or a multi-gate geometry embracing the active region. As seen in Fig 1. these transistor geometries deliver a reduced λ, the thinner the active region thickness tSi is, the higher the dielectric constant is (use of high-k dielectrics) and finally the thinest the gate dielectric thickness tox is. Additionally, the higher degree of embracement of the gate electrode around the semiconductor region is given the smaller λ will be. Ideally, a nanowire or nanoslab geometry completely surrounded by a gate stack delivers the best scalability behavior of MOSFETs.

Figure 1. Potential ϕ(x) perturbation alo ng the channel length for different FET geometries as described by the natural length . a) Natural length expressions for three different channel and gate geometries: Single gated SOI, double gated SOI and surround gated nanowire. The dashed line shows the direction where   is calculated. b) Typical decay of potential over distance x from source along the channel length for different geometries in a). The screening length is the distance where the potential decays to the value of 1/e times of the initial value. Surround gate nanowire offers the l best gate control over the channel, amongst all other implementations. From [1].

Figure 2. More Moore nano-CMOS demonstrators. a) Recessed channel

The research experience of W. M. Weber started 2002 at the Infineon Technologies AG – Corporate Research Labs in Munich, Germany in the Nanodevices group of Dr. Lothar Risch with nanometer-scale top-down nanofabrication as well as semiconductor device technology of ultrathin-body silicon on insulator and multi-gate FETs. Thereto important contributions to build the worldwide first bonded planar double gate transistor [2] –Fig.2-,fully depleted SOI FETs (FDSOI) – Fig. 3a- [3]  and trigate-finFETs. Moreover,  the enhanced gate electrostatics enabled trigate-finFET and nanowire FET flash memory cells with dual-bit operability [4-5].

Figure 3. More Moore nano-CMOS demonstrators. a) Recessed channel SOI MOSFET, b) Trigate fin-NAND flash memory cells IEDM 2006.

Complete pdf-version., opens a file in a new window

Literature:

• [1] W. M. Weber et al. “Silicon and Germanium Nanowire Electronics: Physics of Conventional and Unconventional Transistors” Reports on Progress in Physics  (ROPP) 80, 066502 (50pp) (2017)
• [2] G. Ilicali et al., “Planar double gate transistors with asymmetric independent gates,” in SOI Conference, 2005. Proceedings. 2005 IEEE International, 2005, pp. 126–127.
• [3] L. Dreeskornfeld et al., “Fabrication of ultra-thin-film SOI transistors using the recessed channel concept,” Microelectron. Eng., vol. 78–79, no. 0, pp. 224–228, Mar. 2005.
• [4] C. Friederich et al., “Multi-level p+ tri-gate SONOS NAND string arrays,” in Electron Devices Meeting, 2006. IEDM ’06. International, 2006, pp. 1–4.
• [5] M. Specht et al., “Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications,” in 2004 Symposium on VLSI Technology, 2004. Digest of Technical Papers, 2004, pp. 244–245.
• [6] M. Specht et al., “Novel dual bit tri-gate charge trapping memory devices,” IEEE Electron Device Lett., vol. 25, no. 12, pp. 810–812, Dec. 2004.