Reconfigurable Electronics
Reconfigurable Electroncs:
Emerging electronic systems in the field of data intensive applications such as Edge Computing and the Internet of Things (IoT) pose stringent demands in the computing power and energy efficiency of underlying integrated circuits. For these tasks the conventional CMOS scaling technology is reaching its outermost power consumption and performance limits and the von Neumann Computing Architecture is imposing a latency bottleneck in data transfer between memory and logic units. To leverage computational power beyond those limits the research field of Reconfigurable Electronics explores computational enhancement by extending the functionality of the basic switching units – the transistors – and thereby reinventing circuit topologies and memory-logic interaction.
Figure1. Reconfigurable silicon nanowire field effect transistor (RFET) implemented in a reconfigurable complementary inverter. RFETs reduce the complexity of n- and p-type FETs into a single and thus universal programmable transistor. Through strain engineering symmetric IV characteristics for n- and p-program can be achieved.
A promising Reconfigurable Electronic concept is the reconfigurable nanowire field effect transistor (RFET) – see Fig. 1– that provides unipolar n- or p-type electrical characteristics at runtime as programmed by an electric select signal. By exploiting reconfiguration at runtime, RFETs enable novel combinational and dynamic circuits that yield a higher number of functions with the same hardware complexity as conventional CMOS electronics. Importantly, RFETs do not require doping and can be entirely fabricated with materials and processes established in volume silicon and / or silicon-germanium CMOS production facilities.
Figure 2. Operation principle of the RFET. a) physical structure with individually gated source (S) and drain (D) electrodes. Schematic band diagram of n- and p- program operation as adjusted by the potential of the program gate (PG) and control gate (CG) electrode.
RFETs were initially proposed and demonstrated by Walter Weber in 2006-2008 in the Infineon, opens an external URL in a new window Technologies AG , opens an external URL in a new windowCorporate Research and later Qimonda AG , opens an external URL in a new windowMaterial Research Laboratories in Munich. Later Weber´s group at NaMLab gGmbH, opens an external URL in a new window in Dresden developed RFETs with strongly enhanced performance [A. Heinzig et al. NanoLett 2012, opens an external URL in a new window] and was the first to demonstrate full circuit capability [A. Heinzig et al. NanoLett 2013, opens an external URL in a new window] through its unique strain engineering approach to adjust the symmetry of the IV characteristics of n- and p-programmed FETs – Fig. 1-. Substantial performance enhancement and reduction in dynamic power consumption has been proposed through the use of germanium and silicon-germanium [J., opens an external URL in a new window Trommer et. al. ACS Nano 2017, opens an external URL in a new window]. Latest developments have shown symmetric SOI based omega gate FETs [M. Simon EDL 2020, opens an external URL in a new window] – Fig. 3- as well as first encouraging integration efforts in an industrial 22 nm FDSOI technology [ESSDERC 2019, opens an external URL in a new window]. Recently, the demonstration of individually addressable non-volatile RFETs with multi-bit operability was undertaken with charge trapping gate stacks [S.J. Park et. al. Adv. Elec. Mater. 2017, opens an external URL in a new window] and HfxZr1-xO2 based ferroelectric gate stacks [V. Sessi et al. Adv. Elec. Mater. 2020, opens an external URL in a new window].
Figure 3. Top-down silicon on insulator (SOI) nanowire technology with omega shaped gate architecture. A recursive self-limited processing provides the controlled shrinkage of the Si nanowire / nanoslab core making diameters of thicknesses of ~ 3.5 nm accessible d) yielding excellent electrostatics and adjusts the required radial compressive stress e). a) Top view and side cross-section b) and d). The NiSi2 source channel Schottky junctions are flat and atomically abrupt enhancing the injection properties c).
At the circuit level the Weber Group at NaMLab showed reconfigurability of NAND / NOR / MIN circuit topologies [J. Trommer et al. EDL 2014, opens an external URL in a new window] – Fig. 4 a-c- as well as XOR / XNOR runtime reconfigurability. [J. Trommer et al. DATE 2016 , opens an external URL in a new window] The RFET work was one of the key projects investigated within the German cluster of excellence Center for Advancing Electronics, opens an external URL in a new window Dresden , opens an external URL in a new window– cfaed–. There a complete and dedicated chain of models, logic circuit libraries, logic circuit synthesis for the automated design of deliberate combinatorial circuits was set up capable of even delivering the final technology layout for circuit fabrication (physical synthesis) -Fig. 4d- [S. Rai et al. DATE 2018, opens an external URL in a new window]. With RFETs efficient multi-bit adders and arithmetic logic units (ALU) have been designed –Fig. 4e.
Figure 4. Reconfigurable circuits made of RFETs. Runtime reconfigurable NAND / NOR / MIN circuit: a) circuit, b) technical realization with a single nanowire, c) electrical performance showing equal delay for NAND and NOR functions, with respective layout in 22 nm FDSOI d). Single-bit arithmetic logic unit (ALU) built of RFETs incl. logic table e).
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Literature:
W. M. Weber. Reconfigurable Silicon Nanowire Devices and Circuits: Opportunities and Challenges. Invited paper IEEE Proc. Design, Automation and Test in Europe (DATE) 2014, opens an external URL in a new window
W. M. Weber, A. Heinzig, J. Trommer, D. Martin, M. Grube and T. Mikolajick. Reconfigurable Nanowire Electronics - A review. Invited paper Solid State Electronics 102, pp. 12-24 (2014), opens an external URL in a new window