As a member of the RISC-V community, TU Wien will also drive the RISC-V community with activities such as co-organizing the RISC-V Summit Europe and various open-source contributions. TU Wiens vision is to explore cutting-edge applications of the RISC-V ISA in various domains, including embedded systems, high-performance computing, and beyond.

RISC-V is an open-source instruction set architecture (ISA) that has gained significant traction in both academic and industrial circles for its flexibility, scalability, and openness. Unlike proprietary ISAs, RISC-V is designed to be extensible, allowing researchers and developers to customize and innovate without licensing restrictions. This makes it particularly attractive for a wide range of applications, from embedded systems to high-performance computing. As a result, RISC-V is fostering a growing ecosystem that promotes collaborative advancements in processor design and computing technologies.

Both, the Institute of Computer Technology and the Institute of Embedded Computing Systems have a strong background in RISC-V and proven track record in industrial collaboration. Past works covered topics such as:

• Fast performance models for RISC-V processors
• compiler extensions to support custom instruction extensions
• Fault injection and fault tolerance methods
• Processor extensions in the domain of Security and EdgeAI applications
• Processor extensions for acceleration units

Students, research and industrial partners who are interested to collaborate on this topic are welcome to reach out to the Institute of Computer Technology or the Institute of Embedded Computing Systems. Also, TU Wien can be found on the Open Hardware Mini Summit, opens an external URL in a new window on Sep. 19 in Vienna.

Contact 

Institute of Computer Technology contact information:

• Axel Jantsch: axel.jantsch@tuwien.ac.at
• Sofia Maragkou: sofia.maragkou@tuwien.ac.at
• Markus Kobelrausch: markus.kobelrausch@tuwien.ac.at

Institute of Computer Engineering contact information:

• Daniel Müller-Gritschneder: daniel.mueller-gritschneder@tuwien.ac.at