Faculty prize for diploma thesis.

The ICT congratulates the Dipl.-Ing. Florian Egert for receiving the Faculty Prize of the Faculty of Electrical Engineering and Information Technology for his diploma thesis: FRANCIS-V: FRAmework for iNtegrating Custom InstructionS into RISC-V systems.

[Translate to English:] Portraitfoto von Florian Egert

ICT, as a new member of the RISC-V, opens an external URL in a new window community, visions to explore innovative applications of RISC-V, opens an external URL in a new window and contribute to the open-source community.


Embedded systems are essential building blocks in nearly every aspect of today’s life. Simultaneously to increasingly tight design requirements, the steady growth of application fields raises the need for versatile systems. Application Specific Instruction Set Processors (ASIPs) offer an efficiency and versatility trade-off by providing a flexible base instruction set extensible with application-specific Custom Instructions (CIs). The emerging open-source architecture RISC-V introduces new challenges to the topic. The RISC-V ecosystem requires tools for automating the tedious CI development process. In particular, there
is a lack of flexible methodologies to facilitate the integration of compatible and reusable components. This thesis proposes FRANCIS-V, an integration framework to reduce the effort required for designing CI-based systems. Its main contribution is a flexible interfacing methodology for coprocessor generation
based on the OpenHW Group’s CORE-V eXtension Interface (XIF), complemented by a predefined RISC-V processor system as well as compilation, simulation, and verification features. The thesis further proposes a comprehensive analysis of the CI development process, recognizing CI identification, hardware generation, integration, and verification as its major challenges. An expert estimation is performed to evaluate the potential development time reduced by utilizing
FRANCIS-V, yielding a reduction of around 16 workdays or 34% of saved total time. The generated systems are further evaluated based on two use cases, AES and CRC. The evaluation yields a considerable cycle count decrease of up to 87.53% and a marginal LUT and FF utilization overhead of 0.85% and 2.75%,
respectively, positioning the framework as competitive to comparable tools. The generated coprocessors support a broad range of CIs and are compatible with XIF-based RISC-V processors. FRANCIS-V contributes to the identified challenges of CI integration and verification, and it is further designed for collaboration with prospective identification and hardware generation solutions. It significantly improves the CI development process for designers with varying expertise. The thesis emphasizes the need for flexible and standardized RISC-V CI interfacing solutions and motivates further work on CI integration and overall CI design automation.

Supervisors: Axel Jantsch, Sofia Maragkou

Thesis, opens an external URL in a new window